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1 ltc1436a ltc1436a-pll/ltc1437a high efficiency low noise synchronous step-down switching regulators figure 1. high efficiency step-down converter features descriptio n u , ltc and lt are registered trademarks of linear technology corporation. adaptive power is a trademark of linear technology corporation. n maintains constant frequency at low output currents n dual n-channel mosfet synchronous drive n programmable fixed frequency (pll lockable) n wide v in range: 3.5v to 36v operation n low minimum on-time ( 300ns) for high frequency, low duty cycle applications n very low dropout operation: 99% duty cycle n low dropout, 0.5a linear regulator for cpu i/o or low noise audio supplies n built-in power-on reset timer n programmable soft start n low-battery detector n remote output voltage sense n foldback current limiting (optional) n pin selectable output voltage n logic controlled micropower shutdown: i q < 25 m a n output voltages from 1.19v to 9v n available in 24-lead narrow ssop and 28-lead ssop packages the ltc ? 1436a/ltc1437a are synchronous step-down switching regulator controllers that drive external n-channel power mosfets in a phase lockable, fixed frequency architecture. the adaptive power tm output stage selectively drives two n-channel mosfets at frequencies up to 400khz while reducing switching losses to maintain high efficiencies at low output currents. an auxiliary 0.5a linear regulator using an external pnp pass device provides a low noise, low dropout voltage source. a secondary winding feedback control pin (sfb) guarantees regulation regardless of the load on the main output by forcing continuous operation. an additional comparator is available for use as a low- battery detector. a power-on reset timer (por) is included which generates a signal delayed by 65536/f clk (300ms typically) after the output is within 5% of the regulated output voltage. internal resistive dividers provide pin selectable output voltages with remote sense capability. the operating current level is user-programmable via an external current sense resistor. wide input supply range allows operation from 3.5v to 30v (36v maximum). applicatio n s u n notebook and palmtop computers, pdas n cellular telephones and wireless modems n portable instruments n battery-operated devices n dc power distribution systems typical applicatio n u c osc run/ss v in v prog + + + v in 4.5v to 22v c b 0.1 f 4.7 f 1000pf ltc1436a m1 si4412dy l1 4.7 h r sense 0.02 c out 100 f 6.3v 2 r1 35.7k r2 102k c in 22 f 35v 2 c osc 43pf c ss 0.1 f c c 510pf 100pf r c 10k v out 1.6v 5a m2 si4412dy d1 mbrs140t3 sense + sense sgnd m3 irlml2803 d b cmdsh-3 tgl tgs sw boost bg pgnd 1436 f01 intv cc i th v osense
2 ltc1436a ltc1436-pll-a/ltc1437a absolute m axi m u m ratings w ww u input supply voltage (v in ).........................36v to C 0.3v topside driver supply voltage (boost) ......42v to C 0.3v switch voltage (sw)............................. v in + 5v to C 5v extv cc voltage .........................................10v to C 0.3v por, lbo voltages ....................................12v to C 0.3v auxfb voltage ..........................................20v to C 0.3v auxdr voltage ..........................................28v to C 0.3v sense + , sense C , v osense voltages.................. intv cc + 0.3v to C 0.3v v prog voltage..................................... intv cc to C 0.3v pll lpf, i th voltages ............................... 2.7v to C 0.3v auxon, pllin, sfb, run/ss, lbi voltages ..........................10v to C 0.3v peak driver output current < 10 m s (tgl, bg) .......... 2a peak driver output current < 10 m s (tgs) ......... 250ma intv cc output current ......................................... 50ma operating temperature range ltc143xac ............................................. 0 c to 70 c ltc143xai ........................................ C 40 c to 85 c junction temperature (note 1) ............................. 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c symbol parameter conditions min typ max units main control loop i in v osense feedback current v prog pin open (note 2) 10 50 na v out regulated output voltage (note 2) 1.19v (adjustable) selected v prog pin open l 1.178 1.19 1.202 v 3.3v selected v prog = 0v l 3.220 3.30 3.380 v 5v selected v prog = intv cc l 4.900 5.00 5.100 v t a = 25 c, v in = 15v, v run/ss = 5v unless otherwise noted. electrical characteristics package/order i n for m atio n w u u order part number 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead plastic ssop (150 mil ssop) 24 23 22 21 20 19 18 17 16 15 14 13 pll lpf c osc run/ss i th sfb sgnd v prog v osense sense sense + auxon auxfb pllin por boost tgl sw tgs v in intv cc bg pgnd extv cc auxdr order part number t jmax = 125 c, q ja = 95 c/w top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pll lpf c osc run/ss lbo lbi i th sfb sgnd v prog v osense nc sense sense + auxon pllin por boost tgl sw tgs v in intv cc drv cc bg pgnd extv cc auxdr auxfb order part number 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead plastic ssop (150 mil ssop) 24 23 22 21 20 19 18 17 16 15 14 13 c osc run/ss lbo lbi i th sfb sgnd v prog v osense sense sense + auxon por boost tgl sw tgs v in intv cc bg pgnd extv cc auxdr auxfb t jmax = 125 c, q ja = 110 c/w t jmax = 125 c, q ja = 110 c/w consult factory for military grade parts. ltc1436acgn ltc1436aign ltc1436acgn-pll LTC1436AIGN-PLL ltc1437acg ltc1437aig
3 ltc1436a ltc1436a-pll/ltc1437a electrical characteristics t a = 25 c, v in = 15v, v run/ss = 5v unless otherwise noted. symbol parameter conditions min typ max units v linereg reference voltage line regulation v in = 3.6v to 20v (note 2), v prog pin open 0.002 0.01 %/v v loadreg output voltage load regulation i th sinking 5 m a (note 2) l 0.5 0.8 % i th sourcing 5 m a (note 2) l C 0.5 C 0.8 % v sfb secondary feedback threshold v sfb ramping negative l 1.16 1.19 1.22 v i sfb secondary feedback current v sfb = 1.5v C 1 C 2 m a v ovl output overvoltage lockout v prog pin open 1.24 1.28 1.32 v i prog v prog input current 0.5v > v prog C3 C6 m a intv cc C 0.5v < v prog < intv cc 3 6 m a i q input dc supply current extv cc = 5v (note 3) normal mode 3.6v < v in < 30v, v auxon = 0v 280 m a shutdown v run/ss = 0v, 3.6v < v in < 15v 16 25 m a v run/ss run pin threshold l 0.8 1.3 2 v i run/ss soft start current source v run/ss = 0v 1.5 3 4.5 m a d v sense(max) maximum current sense threshold v osense = 0v, 5v, v prog pin open 130 150 180 mv t on(min) minimum on-time tested with square wave, sense C = 1.6v, 250 300 ns d v sense = 20mv (note 6) tgl transition time tgl t r rise time c load = 3000pf 50 150 ns tgl t f fall time c load = 3000pf 50 150 ns tgs transition time tgs t r rise time c load = 500pf 90 200 ns tgs t f fall time c load = 500pf 50 150 ns bg transition time bg t r rise time c load = 3000pf 50 150 ns bg t f fall time c load = 3000pf 40 150 ns internal v cc regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v l 4.8 5.0 5.2 v v ldo int intv cc load regulation i intvcc = 15ma, v extvcc = 4v C 0.2 C 1 % v ldo ext extv cc voltage drop i intvcc = 15ma, v extvcc = 5v 130 230 mv v extvcc extv cc switchover voltage i intvcc = 15ma, v extvcc ramping positive l 4.5 4.7 v oscillator and phase-locked loop f osc oscillator frequency c osc = 100pf, ltc1436 (note 4), 112 125 138 khz ltc1436a-pll/ltc1437a, v plllpf = 0v vco high ltc1436a-pll/ltc1437a, v plllpf = 2.4v 200 240 khz r pllin pll in input resistance 50 k w i plllpf phase detector output current sinking capability f pllin < f osc 10 15 20 m a sourcing capability f pllin > f osc 10 15 20 m a power-on reset v satpor por saturation voltage i por = 1.6ma, v osense = 1v, v prog pin open 0.6 1 v i lpor por leakage v por = 12v, v osense = 1.2v, v prog pin open 0.2 1 m a v thpor por trip voltage v prog pin open, v osense ramping negative C 11 C 7.5 C 4 % t dpor por delay v prog pin open 65536 cycles
4 ltc1436a ltc1436-pll-a/ltc1437a electrical characteristics t a = 25 c, v in = 15v, v run/ss = 5v unless otherwise noted. symbol parameter conditions min typ max units low-battery comparator v satlbo lbo saturation voltage i lbo = 1.6ma, v lbi = 1.1v 0.6 1 v i llbo lbo leakage v lbo = 12v, v lbi = 1.4v l 0.01 1 m a v thlbi lbi trip voltage high to low transition on lbo l 1.16 1.19 1.22 v i inlbi lbi input current v lbi = 1.19v l 150 na v hyslbo lbo hysteresis 20 mv auxiliary regulator/comparator i auxdr auxdr current v extvcc = 0v max current sinking capability v auxdr = 4v, v auxfb = 1.0v, v auxon = 5v 10 15 ma control current v auxdr = 5v, v auxfb = 1.5v, v auxon = 5v 1 5 m a leakage when off v auxdr = 24v, v auxfb = 1.5v, v auxon = 0v 0.01 1 m a i in auxfb auxfb input current v auxfb = 1.19v, v auxon = 5v 0.01 1 m a i in auxon auxon input current v auxon = 5v 0.01 1 m a v th auxon auxon trip voltage v auxdr = 4v, v auxfb = 1.0v 1.0 1.19 1.4 v v sat auxdr auxdr saturation voltage i auxdr = 1.6ma, v auxfb = 1.0v, v auxon = 5v 0.4 0.8 v v auxfb auxfb voltage v auxon = 5v, 11v < v auxdr < 24v (note 5) l 11.5 12 12.5 v v auxon = 5v, 3v < v auxdr < 7v (note 5) l 1.14 1.19 1.24 v v th auxdr auxfb divider disconnect voltage v auxon = 5v (note 5), ramping negative 7.5 8.5 9.5 v note 4: oscillator frequency is tested by measuring the c osc charge and discharge currents and applying the formula: f osc (khz) = + ? 8.4(10 8 ) c osc (pf) + 11 () 1 i chg () 1 i dis note 5: the auxiliary regulator is tested in a feedback loop which servos v auxfb to the balance point for the error amplifier. for applications with v auxdr > 9.5v, v auxfb uses an internal resistive divider. see applications information. note 6: the minimum on-time test condition corresponds to an inductor peak-to-peak ripple current 3 40% of i max (see minimum on-time considerations in the applications information section). the l denotes specifications which apply over the full operating temperature range. ltc1436acgn/ltc1436acgn-pll/ltc1437acg: 0 c t a 70 c ltc1436aign/LTC1436AIGN-PLL/ltc1437aig: C 40 c t a 85 c note 1: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc1436acgn/ltc1436acgn-pll/ltc1436aign/ LTC1436AIGN-PLL: t j = t a + (p d )(110 c/w) ltc1437acg/ltc1437aig: t j = t a + (p d )(95 c/w) note 2: the ltc1436a/ltc1437a are tested in a feedback loop which servos v osense to the balance point for the error amplifier (v ith = 1.19v). note 3: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information section.
5 ltc1436a ltc1436a-pll/ltc1437a typical perfor m a n ce characteristics u w efficiency vs input voltage v out = 3.3v v in C v out dropout voltage vs load current efficiency vs load current v ith pin voltage vs output current efficiency vs input voltage v out = 5v load regulation load current (a) 0.001 50 efficiency (%) 55 65 70 75 100 85 0.01 0.1 1 1435 g03 60 90 95 80 10 adaptive power mode continuous mode v in = 10v v out = 5v r sense = 0.033 w burst mode tm operation load current (a) 0 0 v in ?v out (v) 0.2 0.1 0.3 0.4 0.5 0.5 1.0 1.5 2.0 1436 g04 2.5 3.0 r sense = 0.033 w v out drop of 5% load current (a) 0 d v out (%) 0 0.5 1.0 1.5 2.0 1436 g05 2.5 3.0 0.25 0.50 0.75 ?.00 ?.25 ?.50 r sense = 0.033 w output current (%) 0 v ith (v) 1.0 2.0 3.0 0.5 1.5 2.5 20 40 60 80 1436 g06 100 10 030507090 burst mode operation continuous/adaptive power mode input supply current vs input voltage extv cc switch drop vs intv cc load current input voltage (v) 0 0 supply current (ma) shutdown current ( m a) 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 5 10 15 20 1436 g07 25 30 v out = 3.3v extv cc = open v out = 5v extv cc = v out shutdown intv cc regulation vs intv cc load current intv cc load current (ma) 0 d intv cc (%) 0 0.3 20 1436 g08 0.3 0.5 5 10 70 c 25 c 15 0.5 v extvcc = 0v intv cc load current (ma) 0 extv cc ?intv cc (mv) 120 160 200 16 1436 g09 80 40 100 140 180 60 20 0 4 8 12 218 6 10 14 20 ?5 c 25 c 70 c burst mode is a trademark of linear technology corporation. input voltage (v) 0 70 efficiency (%) 75 80 85 90 100 5 10 15 20 1436 g02 25 30 95 i load = 1a i load = 100ma v out = 5v input voltage (v) 0 70 efficiency (%) 75 80 85 90 100 5 10 15 20 1436 g01 25 30 95 i load = 1a i load = 100ma v out = 3.3v
6 ltc1436a ltc1436-pll-a/ltc1437a typical perfor m a n ce characteristics u w temperature ( c) ?0 frequency (%) 5 10 35 85 1436 g10 f o ?5 10 60 110 135 ? ?0 normalized oscillator frequency vs temperature transient response transient response maximum current sense threshold voltage vs temperature i load = 50ma to 1a 1436 g14 i load = 1a to 3a 1436 g15 temperature ( c) ?0 0 run/ss current ( m a) 1 2 3 4 ?5 10 35 60 1436 g11 85 110 135 run/ss pin current vs temperature temperature ( c) ?0 146 current sense threshold (mv) 148 150 152 154 ?5 10 35 60 1436 g13 85 110 135 v out 50mv/div v out 50mv/div v out 20mv/div v ith 200mv/div i load = 50ma 1436 g16 burst mode operation auxiliary load current (ma) 0 auxiliary output voltage (v) 12.0 12.1 12.2 160 1436 g18 11.9 11.8 11.7 40 80 120 200 external pnp: 2n2907a auxiliary regulator load regulation sfb pin current vs temperature temperature ( c) ?0 sfb current ( m a) ?.50 0.25 0 35 85 1436 g12 0.75 ?.00 ?5 10 60 110 135 ?.25 ?.50 soft start: load current vs time 1436 g17 run/ss 5v/div inductor current 1a/div
7 ltc1436a ltc1436a-pll/ltc1437a typical perfor m a n ce characteristics u w auxiliary regulator sink current available aux dr voltage (v) 0 0 aux dr current (ma) 5 10 15 20 2468 1436 g19 10 12 14 16 auxiliary regulator psrr frequency (khz) 10 10 20 30 40 50 60 70 psrr (db) 100 1000 1436 g20 10ma load 100ma load pi n fu n ctio n s uuu v in : main supply pin. must be closely decoupled to the ics signal ground pin. intv cc : output of the internal 5v regulator and extv cc switch. the driver and control circuits are powered from this voltage. must be closely decoupled to power ground with a minimum of 2.2 m f tantalum or electrolytic capacitor. drv cc : bottom mosfet driver supply voltage. extv cc : input to the internal switch connected to intv cc . this switch closes and supplies v cc power whenever extv cc is higher than 4.7v. see extv cc connection in applications information section. do not exceed 10v on this pin. connect to v out if v out 3 5v. boost: supply to topside floating driver. the bootstrap capacitor is returned to this pin. voltage swing at this pin is from intv cc to v in + intv cc . sw: switch node connection to inductor. voltage swing at this pin is from a schottky diode (external) voltage drop below ground to v in . sgnd: small signal ground. must be routed separately from other grounds to the (C) terminal of c out . pgnd: driver power ground. connects to source of bottom n-channel mosfet and the (C) terminal of c in . sense C : the (C) input to the current comparator. sense + : the (+) input to the current comparator. built- in offsets between sense C and sense + pins in conjunction with r sense set the current trip thresholds. v osense : receives the remotely sensed feedback voltage either from the output or from an external resistive divider across the output . the v prog pin determines which point v osense must connect to. v prog : this voltage selects the output voltage. for v prog < v intvcc /3 the output is set to 3.3v with v osense connected to the output. with v prog > v intvcc /1.5 the output is set to 5v with v osense connected to the output. leaving v prog open (dc) allows the output voltage to be set by an external resistive divider connected to v osense . c osc : external capacitor c osc from this pin to ground sets the operating frequency. i th : error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is 0v to 2.5v. run/ss: combination of soft start and run control inputs. a capacitor to ground at this pin sets the ramp time to full current output. the time is approximately 0.5s/ m f.
8 ltc1436a ltc1436-pll-a/ltc1437a pi n fu n ctio n s uuu forcing this pin below 1.3v causes the device to be shut down. in shutdown all functions are disabled. tgl: high current gate drive for main top n-channel mosfet. this is the output of a floating driver with a voltage swing equal to intv cc superimposed on the switch node voltage sw. tgs: high current gate drive for a small top n-channel mosfet. this is the output of a floating driver with a voltage swing equal to intv cc superimposed on the switch node voltage sw. leaving tgs open invokes burst mode operation at low load currents. bg: high current gate drive for bottom n-channel mosfet. voltage swing at this pin is from ground to intv cc (drv cc ). sfb: secondary winding feedback input. normally connected to a feedback resistive divider from the secondary winding. this pin should be tied to: ground to force continuous operation; intv cc in applications that dont use a secondary winding; and a resistive divider from the output in applications using a secondary winding. por : open drain output of an n-channel pull-down. this pin sinks current when the output voltage is 7.5% out of regulation and releases 65536 oscillator cycles after the output voltage rises to C 5% of its regulated value. the por output is asserted when run/ss is low independent of v out . lbo: open drain output of an n-channel pull-down. this pin will sink current when the lbi pin goes below 1.19v. lbi: the (+) input of the low battery voltage comparator. the (C) input is connected to a 1.19v reference. pllin: external synchronizing input to phase detector. this pin is internally terminated to sgnd with 50k w . tie this pin to sgnd in applications which do not use the phase-locked loop. pll lpf: output of phase detector and control input of oscillator. normally a series rc lowpass filter network is connected from this pin to ground. tie this pin to sgnd in applications which do not use the phase-locked loop. can be driven by 0v to 2.4v logic signal for a frequency shifting option. auxfb: feedback input to the auxiliary regulator/ comparator. when used as a linear regulator, this input can either be connected to an external resistive divider or directly to the collector of the external pnp pass device for 12v operation. when used as a comparator, this is the noninverting input of a comparator whose inverting input is tied to the internal 1.19v reference. see auxiliary regulator/comparator in applications information section. auxon: pulling this pin high turns on the auxiliary regulator/ comparator. the threshold is 1.19v. auxdr: open drain output of the auxiliary regulator/ comparator. the base of an external pnp device is connected to this pin for use as a linear regulator. an external pull-up resistor is required for use as a comparator. a voltage > 9.5v on auxdr causes the internal 12v resistive divider to be connected to auxfb.
9 ltc1436a ltc1436a-pll/ltc1437a fu n ctio n al diagra uu w + + + + 12v out auxon auxdr por pllin* pll lpf* 2.4v r lp c osc sfb 1.10v 1.28v v fb 1.19v 320k 61k 119k 1.19v run/ss c ss c c ov 1.19v 0.6v i2 4k intv cc v in pgnd bg drv cc c out c sec v sec c b c in v in d b v out intv cc c intvcc sw d1 1436 fd tgs tgl m1 m3 m2 boost shutdown shutdown 1 m a 3 m a 6v 30k 180k r c i th d fb ? sense + extv cc connection for ltc1436a/ltc1436a-pll sense 8k 4.8v auxfb intv cc v prog v osense sgnd lbo** lbi** * ltc1436a-pll/ltc1437a only ** ltc1436a/ltc1437a only ? foldback current limiting option 1.19v 90.8k 10k 50k 9v c out2 + + aux pwr-on reset phase detector dropout detector osc c osc v in intv cc c lp s r q + + r sense 1.19v ref switch logic + + i1 + + + + + + 5v ldo ref run/ soft start ea g m = 1m w
10 ltc1436a ltc1436-pll-a/ltc1437a operatio u (refer to functional diagram) main control loop the ltc1436a/ltc1437a use a constant frequency, cur- rent mode step-down architecture. during normal opera- tion, the top mosfet is turned on each cycle when the oscillator sets the rs latch and turned off when the main current comparator i1 resets the rs latch. the peak inductor current at which i1 resets the rs latch is con- trolled by the voltage on i th pin, which is the output of error amplifier ea. v prgm and v osense pins, described in the pin functions, allow ea to receive an output feedback voltage v fb from either internal or external resistive dividers. when the load current increases, it causes a slight decrease in v fb relative to the 1.19v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current compara- tor i2, or the beginning of the next cycle. the top mosfet drivers are biased from floating boot- strap capacitor c b , which normally is recharged during each off cycle. however, when v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detec- tor counts the number of oscillator cycles that the top mosfet remains on, and periodically forces a brief off period to allow c b to recharge. the main control loop is shut down by pulling run/ss pin low. releasing run/ss allows an internal 3 m a current source to charge soft start capacitor c ss . when c ss reaches 1.3v, the main control loop is enabled with the i th voltage clamped at approximately 30% of its maximum value. as c ss continues to charge, i th is gradually re- leased allowing normal operation to resume. comparator ov guards against transient overshoots > 7.5% by turning off the top mosfet and keeping it off until the fault is removed. low current operation adaptive power mode allows the ltc1436a/ltc1437a to automatically change between two output stages sized for different load currents. tgl and bg pins drive large synchronous n-channel mosfets for operation at high currents, while the tgs pin drives a much smaller n-channel mosfet used in conjunction with a schottky diode for operation at low currents. this allows the loop to continue to operate at normal frequency as the load current decreases without incurring the large mosfet gate charge losses. if the tgs pin is left open, the loop defaults to burst mode operation in which the large mosfets operate intermittently based on load demand. adaptive power mode provides constant frequency opera- tion down to approximately 1% of rated load current. this results in an order of magnitude reduction of load current before burst mode operation commences. without the small mosfet (i.e.: no adaptive power mode), the transi- tion to burst mode operation is approximately 10% of rated load current. the transition to low current operation begins when com- parator i2 detects current reversal and turns off the bottom mosfet. if the voltage across r sense does not exceed the hysteresis of i2 (approximately 20mv) for one full cycle, then on following cycles the top drive is routed to the small mosfet at tgs pin and bg pin is disabled. this continues until an inductor current peak exceeds 20mv/ r sense or the i th voltage exceeds 0.6v, either of which causes drive to be returned to tgl pin on the next cycle. two conditions can force continuous synchronous opera- tion, even when the load current would otherwise dictate low current operation. one is when the common mode voltage of the sense + and sense C pins is below 1.4v and the other is when the sfb pin is below 1.19v. the latter condition is used to assist in secondary winding regulation as described in the applications information section. frequency synchronization a phase-locked loop (pll) is available on the ltc1436a-pll and ltc1437a to allow the oscillator to be synchronized to an external source connected to the pllin pin. the output of the phase detector at the pll lpf pin is also the control input of the oscillator, which operates over a 0v to 2.4v range corresponding to C 30% to 30% in frequency. when locked, the pll aligns the turn- on of the top mosfet to the rising edge of the synchroniz- ing signal. when pllin is left open or at a constant dc voltage, pll lpf goes low, forcing the oscillator to mini- mum frequency.
11 ltc1436a ltc1436a-pll/ltc1437a operatio u (refer to functional diagram) power-on reset the por pin is an open drain output which pulls low when the main regulator output voltage is out of regulation. when the output voltage rises to within 7.5% of regula- tion, a timer is started which releases por after 2 16 (65536) oscillator cycles. in shutdown, the por output is pulled low. auxiliary linear regulator the auxiliary linear regulator in the ltc1436a/ltc1437a controls an external pnp transistor for operation up to 500ma. an internal auxfb resistive divider set for 12v operation is invoked when auxdr pin is above 9.5v to allow 12v vpp supplies to be easily implemented. when auxdr is below 8.5v an external feedback divider may be used to set other output voltages. taking the auxon pin low shuts down the auxiliary regulator providing a conve- nient logic controlled power supply. the aux block can be used as a comparator having its inverting input tied to the internal 1.19v reference. the auxdr pin is used as the output and requires an external pull-up to a supply less than 8.5v in order to inhibit the invoking of the internal resistive divider. intv cc /drv cc /extv cc power power for the top and bottom mosfet drivers and most of the other ltc1436a/ltc1437a circuitry is derived from the intv cc pin. the bottom mosfet driver supply drv cc pin is internally connected to intv cc in the ltc1436a and externally connected to intv cc in the ltc1437a. when the extv cc pin is left open, an internal 5v low dropout regulator supplies intv cc power. if extv cc is taken above 4.8v, the 5v regulator is turned off and an internal switch is turned on to connect extv cc to intv cc . this allows the intv cc power to be derived from a high efficiency external source such as the output of the regulator itself or a secondary winding, as described in the applications infor- mation section. applicatio n s i n for m atio n wu u u the basic ltc1436a application circuit is shown in figure 1, high efficiency step-down converter. external compo- nent selection is driven by the load requirement, and begins with the selection of r sense . once r sense is known, c osc and l can be chosen. next, the power mosfets and d1 are selected. finally, c in and c out are selected. the circuit shown in figure 1 can be configured for operation up to an input voltage of 28v (limited by the external mosfets). r sense selection for output current r sense is chosen based on the required output current. the ltc1436a/ltc1437a current comparator has a maxi- mum threshold of 150mv/r sense and an input common mode range of sgnd to intv cc . the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current d i l . allowing a margin for variations in the ltc1436a/ ltc1437a and external component values yields: r mv sense max = 100 i the ltc1436a/ltc1437a work well with r sense values 3 0.005 w . c osc selection for operating frequency the ltc1436a/ltc1437a use a constant frequency architecture with the frequency determined by an external oscillator capacitor c osc . each time the topside mosfet turns on, the voltage on c osc is reset to ground. during the on-time, c osc is charged by a fixed current plus an additional current which is proportional to the output voltage of the phase detector v plllpf (ltc1436a-pll/ ltc1437a). when the voltage on the capacitor reaches 1.19v, c osc is reset to ground. the process then repeats. the value of c osc is calculated from the desired operating frequency. assuming the phase-locked loop has no exter- nal oscillator input (v plllpf = 0v):
12 ltc1436a ltc1436-pll-a/ltc1437a applicatio n s i n for m atio n wu u u operating frequency (khz) c osc value (pf) 300 250 200 150 100 50 0 100 200 300 400 1436 f02 500 0 v plllpf = 0v figure 2. timing capacitor value inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current d i l decreases with higher induc- tance or frequency and increases with higher v in or v out : cpf frequency khz osc () = () ? ? 13710 11 4 .( ) a graph for selecting c osc vs frequency is given in figure 2. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the maximum recommended switching frequency is 400khz. when using figure 2 for synchronizable applications, choose c osc correspond- ing to a frequency approximately 30% below your center frequency. (see phase-locked loop and frequency syn- chronization.) for low duty cycle, high frequency applications where the required minimum on-time, t v vf on min out in max () () = ()() is less than 350ns, there may be further restrictions on the inductance to ensure proper operation. see minimum on- time considerations section for more details. operating frequency (khz) 0 inductor value ( h) 60 50 40 30 20 10 0 50 100 150 200 1436 f03 250 300 v out = 5v v out = 3.3v v out 2.5v figure 3. recommended inductor values d i fl v v v l out out in = ()( ) - ? ? ? ? 1 1 accepting larger values of d i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is d i l = 0.4 (i max ). remember, the maximum d i l occurs at the maximum input voltage. the inductor value also has an effect on low current operation. the transition to low current operation begins when the inductor current reaches zero while the bottom mosfet is on. lower inductor values (higher d i l ) will cause this to occur at higher load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation (tgs pin open), lower inductance values will cause the burst frequency to decrease. the figure 3 graph gives a range of recommended induc- tor values vs operating frequency and v out .
13 ltc1436a ltc1436a-pll/ltc1437a applicatio n s i n for m atio n wu u u frequency operation down to lower currents before cycle skipping occurs. the r ds(on) recommended for the small mosfet is around 0.5 w . be careful not to use a mosfet with an r ds(on) that is too low; remember, we want to conserve gate charge. (a higher r ds(on) mosfet has a smaller gate capacitance and thus requires less current to charge its gate). for cost sensitive applications the small mosfet can be removed. the circuit will then begin burst mode operation as the load current is dropped. the peak-to-peak gate drive levels are set by the intv cc voltage. this voltage is typically 5v during start-up (see extv cc pin connection). consequently, logic level threshold mosfets must be used in most ltc1436a/ ltc1437a applications. the only exception is applications in which extv cc is powered from an external supply greater than 8v (must be less than 10v), in which standard threshold mosfets [v gs(th) < 4v] may be used. pay close attention to the bv dss specification for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r sd(on) , reverse transfer capacitance c rss , input voltage and maximum output current. when the ltc1436a/ltc1437a are operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v v out in synchronous switch duty cycle = v in - () v v out in kool m m is a registered trademark of magnetics, inc. p v v ir kv i c f p vv v ir main out in max ds on in max rss sync in out in max ds on = () + () + () ( )( )() = - () + () () () 2 185 2 1 1 d d . inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are prefered at high switching frequencies, so design goals can concen- trate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m m . toroids are very space efficient, especially when you can use several layers of wire. because they generally lack a bobbin, mounting is more difficult. however, designs for surface mount are available which do not increase the height significantly. power mosfet and d1 selection three external power mosfets must be selected for use with the ltc1436a/ltc1437a: a pair of n-channel mos- fets for the top (main) switch and an n-channel mosfet for the bottom (synchronous) switch. to take advantage of the adaptive power output stage, two topside mosfets must be selected. a large (low r sd(on) ) mosfet and a small (higher r ds(on) ) mosfet are required. the large mosfet is used as the main switch and works in conjunction with the synchronous switch. the smaller mosfet is only enabled under low load current conditions. this increases midcurrent efficiencies while continuing to operate at constant frequency. also, by using the small mosfet the circuit can maintain constant the mosfet power dissipations at maximum output current are given by:
14 ltc1436a ltc1436-pll-a/ltc1437a applicatio n s i n for m atio n wu u u this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. the selection of c out is driven by the required effective series resistance (esr). typically, once the esr require- ment is satisified, the capacitance is adequate for filtering. the output ripple ( d v out ) is approximated by: dd v i esr fc out l out ?+ ? ? ? ? 1 4 where f = operating frequency, c out = output capacitance and d i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. with d i l = 0.4i out(max) the output ripple will be less than 100mv at maximum v in , assuming: c out required esr < 2r sense manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr (size) product of any aluminum electrolytic at a somewhat higher price. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. in surface mount applications multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum elec- trolytic and dry tantalum capacitors are both available in surface mount configurations. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. other capacitor types where d is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transi- tion losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actual provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage or during a short circuit when the duty cycle in this switch is nearly 100%. refer to the foldback current limiting section for further applications information. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mosfet characteristics. the constant k = 2.5 can be used to estimate the contributions of the two terms in the main switch dissipation equation. the schottky diode d1 shown in figure 1 serves two purposes. during continuous synchronous operation, d1 conducts during the dead-time between the conduction of the two large power mosfets. this prevents the body diode of the bottom mosfet from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. during low current operation, d1 oper- ates in conjunction with the small top mosfet to provide an efficient low current output stage. a 1a schottky is generally a good compromise for both regions of opera- tion due to the relatively small average current. c in and c out selection in continuous mode, the source current of the top n-channel mosfet is a square wave of duty cycle v out / v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ci vvv v in max out in out in required i rms ? - () [] 12 /
15 ltc1436a ltc1436a-pll/ltc1437a applicatio n s i n for m atio n wu u u include sanyo os-con, nichicon pl series and sprague 593d and 595d series. consult the manufacturer for other specific recommendations. intv cc regulator an internal p-channel low dropout regulator produces the 5v supply that powers the drivers and internal circuitry within the ltc1436a/ltc1437a. the intv cc pin can supply up to 15ma and must be bypassed to ground with a minimum of 2.2 m f tantalum or low esr electrolytic. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers. high input voltage applications, in which large mosfets are being driven at high frequencies, may cause the maximum junction temperature rating for the ltc1436a/ ltc1437a to be exceeded. the ic supply current is dominated by the gate charge supply current when not using an output derived extv cc source. the gate charge is dependent on operating frequency as discussed in the efficiency considerations section. the junction tempera- ture can be estimated by using the equations given in note 1 of the electrical characteristics. for example, the ltc1437a is limited to less than 19ma from a 30v supply: tvcwc j = 70 c + 19ma ()() () = 30 95 124 / to prevent maximum junction temperature from being exceeded, the input supply current must be checked when operating in continuous mode at maximum v in . extv cc connection the ltc1436a/ltc1437a contain an internal p-channel mosfet switch connected between the extv cc and intv cc pins. the switch closes and supplies the intv cc power whenever the extv cc pin is above 4.8v, and remains closed until extv cc drops below 4.5v. this allows the mosfet driver and control power to be derived from the output during normal operation (4.8v < v out < 9v) and from the internal regulator when the output is out of regulation (start-up, short circuit). do not apply greater than 10v to the extv cc pin and ensure that extv cc < v in . significant efficiency gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of duty cycle / efficiency. for 5v regulators this supply means connecting the extv cc pin directly to v out . however, for 3.3v and other lower voltage regulators, additional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5v regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest efficiency. 3. extv cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage which has been boosted to greater than 4.8v. this can be done with either the inductive boost winding as shown in figure 4a or the capacitive charge pump shown in figure 4b. the charge pump has the advantage of simple magnetics. 4. extv cc connected to an external supply. if an external supply is available in the 5v to 10v range (extv cc < v in ), it may be used to power extv cc , providing it is compatible with the mosfet gate drive requirements. when driving standard threshold mosfets, the exter- nal supply must always be present during operation to prevent mosfet failure due to insufficient gate drive. figure 4a. secondary output loop and extv cc connection r6 r5 extv cc v in tgl tgs sw bg pgnd ltc1436a ltc1437a n-ch n-ch n-ch + c in v in 1n4148 + 1 f + c out v sec t1 1:n r sense v out optional extv cc connection 5v v sec 9v 1436 f04a sfb sgnd
16 ltc1436a ltc1436-pll-a/ltc1437a applicatio n s i n for m atio n wu u u topside mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet(s). capacitor c b in the functional diagram is charged through diode d b from intv cc when the sw pin is low. when one of the topside mosfet(s) is to be turned on, the driver places the c b voltage across the gate source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage sw rises to v in and the boost pin rises to v in + intv cc . the value of the boost capacitor c b needs to be 100 times greater than the total input capacitance of the topside mosfet(s). in most applications 0.1 m f is adequate. the reverse breakdown on d b must be greater than v in(max). output voltage programming the output voltage is pin selectable for all members of the ltc1436a/ltc1437a family. the output voltage is selected by the v prog pin as follows: v prog = 0v v out = 3.3v v prog = intv cc v out = 5v v prog = open (dc) v out = adjustable the ltc1436a/ltc1437a family also has remote output voltage sense capability. the top of an internal resistive divider is connected to v osense . for fixed 3.3v and 5v output voltage applications the v osense pin is connected to the output voltage as shown in figure 5a. when using an external resistive divider, the v prog pin is left open (dc) and the v osense pin is connected to the feedback resistors as shown in figure 5b. figure 4b. capacitive charge pump for ext v cc figure 5b. ltc1436a/ltc1437a adjustable applications figure 5a. ltc1436a/ltc1437a fixed output applications power-on reset function (por) the power-on reset function monitors the output voltage and turns on an open drain device when it is out of regulation. an external pull-up resistor is required on the por pin. when power is first applied or when coming out of shutdown, the por output is pulled to ground. when the output voltage rises above a level which is 5% below the final regulated output value, an internal counter starts. after counting 2 16 (65536) clock cycles, the por pull- down device turns off. the por output will go low whenever the output voltage drops below 7.5% of its regulated value for longer than approximately 30 m s, signaling an out-of-regulation condi- tion. in shutdown, the por output is pulled low even if the regulators output is held up by an external source. run/soft start function the run/ss pin is a dual purpose pin that provides the soft start function and a means to shut down the ltc1436a/ltc1437a. soft start reduces surge currents from v in by gradually increasing the internal current limit. power supply sequencing can also be accomplished using this pin. extv cc v in tgl tgs sw bg pgnd ltc1436a ltc1437a n-ch n-ch n-ch + c in v in 0.22 m f bat85 bat85 c out bat85 + 1 f + l1 r sense vn2222ll 1436 f04b v prog sgnd ltc1436a ltc1437a 1436 f05a c out v out gnd: v out = 3.3v intv cc : v out = 5v + v osense r1 r2 open (dc) 1436 f05b 100pf 1.19v v out 9v v prog sgnd ltc1436a ltc1437a v osense v out = 1.19v 1 + r2 r1 ()
17 ltc1436a ltc1436a-pll/ltc1437a applicatio n s i n for m atio n wu u u an internal 3 m a current source charges up an external capacitor c ss. when the voltage on run/ss reaches 1.3v the ltc1436a/ltc1437a begin operating. as the voltage on run/ss continues to ramp from 1.3v to 2.4v, the internal current limit is also ramped at a proportional linear rate. the current limit begins at approximately 50mv/ r sense (at v run/ss = 1.3v) and ends at 150mv/r sense (v run/ss > 2.7v). the output current thus ramps up slowly, charging the output capacitor. if run/ss has been pulled all the way to ground there is a delay before starting of approximately 500ms/ m f, followed by an additional 500ms/ m f to reach full current. t delay = 5(10 5 )c ss seconds pulling the run/ss pin below 1.3v puts the ltc1436a/ ltc1437a into a low quiescent current shutdown (i q < 25 m a). this pin can be driven directly from logic as shown in figure 6. diode d1 in figure 6 reduces the start delay but allows c ss to ramp up slowly for the soft start function; this diode and c ss can be deleted if soft start is not needed. the run/ss pin has an internal 6v zener clamp (see functional diagram). foldback current limiting is implemented by adding a diode d fb between the output and i th pins as shown in the function diagram. in a hard short (v out = 0v), the current will be reduced to approximately 25% of the maximum output current. this technique may be used for all applica- tions with regulated output voltages of 1.8v or greater. phase-locked loop and frequency synchronization the ltc1436a-pll/ltc1437a each have an internal volt- age- controlled oscillator and phase detector comprising a phase-locked loop. this allows the top mosfet turn-on to be locked to the rising edge of an external source. the frequency range of the voltage-controlled oscillator is 30% around the center frequency f o . the value of c osc is calculated from the desired operating frequency f o . assuming the phase-locked loop is locked (v plllpf = 1.19v): c frequency osc pf khz () = () ? ? 2110 11 4 .( ) stating the frequency as a function of v plllpf and c osc : frequency khz cpf aa v v osc plllpf () = () + [] + ? ? ? ? + ? ? 8410 11 1 17 18 24 2000 8 .( ) . mm the phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. this type of phase detec- tor will not lock up on input frequencies close to the harmonics of the vco center frequency. the pll hold-in range d f h is equal to the capture range: d f h = d f c = 0.3f o . foldback current limiting as described in power mosfet and d1 selection, the worst-case dissipation for either mosfet occurs with a short-circuited output, when the synchronous mosfet conducts the current limit value almost continuously. in most applications this will not cause excessive heating, even for extended fault intervals. however, when heat sinking is at a premium or higher r ds(on) mosfets are being used, foldback current limiting should be added to reduce the current in proportion to the severity of the fault. 1436 f06 c ss d1 3.3v or 5v run/ss c ss run/ss figure 6. run/ss pin interfacing
18 ltc1436a ltc1436-pll-a/ltc1437a applicatio n s i n for m atio n wu u u difference. thus the voltage on the pll lpf pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point the phase comparator output is open and the filter capacitor c lp holds the voltage. the loop filter components c lp and r lp smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically, r lp = 10k and c lp is 0.01 m f to 0.1 m f. be sure to connect the low side of the filter to sgnd. the pll lpf pin can be driven with external logic to obtain a 1:1.9 frequency shift. the circuit shown in figure 9 will provide a frequency shift from f o to 1.9f o as the voltage and v plllpf increases from 0v to 2.4v. do not exceed 2.4v on v plllpf . the output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the pll lpf pin. the relationship between the pll lpf pin and operating frequency is shown in figure 7. a simplified block diagram is shown in figure 8. if the external frequency (f pllin ) is greater than the oscil- lator frequency (f), current is sourced continuously, pull- ing up the pll lpf pin. when the external frequency is less than f osc , current is sunk continuously, pulling down the pll lpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase figure 7. operating frequency vs v plllpf pll lpf 2.4v max 3.3v or 5v 1436 f09 18k figure 9. directly driving pll lpf pin low-battery comparator the ltc1436a/ltc1437a have an on-chip low-battery comparator which can be used to sense a low-battery condition when implemented as shown in figure 10. the resistive divider r3, r4 sets the comparator trip point as follows: vv r r lbtrip =+ ? ? ? ? 119 1 4 3 . pllin 50k 1436 f08 pll lpf c osc phase detector osc r lp c lp c osc external frequency 2.4v digital phase/ frequency detector v plllpf (v) 0 frequency (khz) 1.3f o 0.7f o 1436 f07 1.5 2.0 1.0 0.5 2.5 f o figure 8. phase-locked loop block diagram figure 10. low battery comparator + lbi v in sgnd lbo r4 r3 1436 f10 1.19v reference ltc1436a ltc1437a
19 ltc1436a ltc1436a-pll/ltc1437a applicatio n s i n for m atio n wu u u the divided down voltage at the negative (C) input to the comparator is compared to an internal 1.19v reference. a 20mv hysteresis is built in to assure rapid switching. the output is an open drain mosfet and requires a pull-up resistor. this comparator is not active in shutdown. the low side of the resistive divider should connect to sgnd. sfb pin operation when the sfb pin drops below its ground-referenced 1.19v threshold, continuous mode operation is forced. in continuous mode, the large n-channel main and synchro- nous switches are used regardless of the load on the main output. in addition to providing a logic input to force continuous synchronous operation, the sfb pin provides a means to regulate a flyback winding output. continuous synchro- nous operation allows power to be drawn from the auxil- iary windings without regard to the primary output load. the sfb pin provides a way to force continuous synchro- nous operation as needed by the flyback winding. the secondary output voltage is set by the turns ratio of the transformer in conjunction with a pair of external resistors returned to the sfb pin as shown in figure 4a. the secondary regulated voltage v sec in figure 4a is given by: vnv v r r sec out ?+ () >+ ? ? ? ? 1 1 19 1 6 5 . where n is the turns ratio of the transformer and v out is the main output voltage sensed by v osense . auxiliary regulator/comparator the auxiliary regulator/comparator can be used as a comparator or low dropout regulator (by adding an exter- nal pnp pass device). when the voltage present at the auxon pin is greater than 1.19v the regulator/comparator is on. special circuitry consumes a small (20 m a) bias current while still remain- ing stable when operating as a low dropout regulator. no excess current is drawn when the input stage is overdriven when used as a comparator. the auxdr pin is internally connected to an open drain mosfet which can sink up to 10ma. the voltage on auxdr determines whether or not an internal 12v resis- tive divider is connected to auxfb as described below. a pull-up resistor is required on auxdr and the voltage must not exceed 28v. with the addition of an external pnp pass device, a linear regulator capable of supplying up to 0.5a is created. as shown in figure 12a, the base of the external pnp con- nects to the auxdr pin together with a pull-up resistor. the output voltage v oaux at the collector of the external pnp is sensed by the auxfb pin. the input voltage to the auxiliary regulator can be taken from a secondary winding on the primary inductor as shown in figure 11a. in this application, the sfb pin regulates the input voltage to the pnp regulator (see sfb pin operation) and should be set to approximately 1v to 2v above the required output voltage of the auxiliary regulator. a zener diode clamp may be required to keep v sec under the 28v auxdr pin specification when the primary is heavily loaded and the secondary is not. the auxfb pin is the feedback point of the regulator. an internal resistive divider is available to provide a 12v output by simply connecting auxfb directly to the collec- tor of the external pnp. the internal resistive divider is selected when the voltage at auxfb goes above 9.5v with 1v built-in hysteresis. for other output voltages, an exter- nal resistive divider is fed back to auxfb as shown in figure 11b. the output voltage v oaux is set as follows: v oaux = 1.19v(1+r8/r7) < 8v auxdr < 8.5v v oaux = 12v auxdr > 12v the circuit can also be used as a noninverting voltage comparator as shown in figure 11c. when auxfb drops below 1.19v, the auxdr pin will be pulled low. a mini- mum current of 5 m a is required to pull the auxdr pin to 5v when used as a comparator output, in order to coun- teract a 1.5 m a internal current source.
20 ltc1436a ltc1436-pll-a/ltc1437a applicatio n s i n for m atio n wu u u figure 11a. 12v output auxiliary regulator using internal feedback resistors the minimum on-time for the ltc1436a/ltc1437a in a properly configured application is less than 300ns but increases at low ripple current amplitudes (see figure 12). if an application is expected to operate close to the minimum on-time limit, an inductor value must be chosen that is low enough to provide sufficient ripple amplitude to meet the minimum on-time requirement. to determine the proper value, use the following procedure: 1. calculate on-time at maximum supply, t on(min) = (1/f)(v out /v in(max) ). 2. use figure 12 to obtain the peak-to-peak inductor ripple current as a percentage of i max necessary to achieve the calculated t on(min) . 3. ripple amplitude d i l(min) = (% from figure 12) (i max ) where i max = 0.1/r sense . 4. l max = t vv i on min in max out l min () () () d ? ? ? ? choose an inductor less than or equal to the calculated l max to ensure proper operation. 1436 f11a v sec = 1.19v 1 + > 13v r6 r5 () on/off v sec secondary winding r6 r5 10 m f 1:n v oaux 12v auxdr ltc1436a ltc1437a auxfb auxon + sfb + figure 11c. auxiliary comparator configuration + auxon auxfb on/off input v pull-up < 8.5v auxdr output 1436 f11c 1.19v reference ltc1436a ltc1437a figure 11b. 5v output auxiliary regulator using external feedback resistors on/off v sec secondary winding r6 r5 r8 r7 1436 f11b 10 m f 1:n v oaux auxdr ltc1436a ltc1437a auxfb auxon v sec = 1.19v 1 + r6 r5 () v oaux = 1.19v 1 + r8 r7 () + sfb + minimum on-time considerations minimum on-time, t on(min) , is the smallest amount of time that the ltc1436a/ltc1437a are capable of turning the top mosfet on and off again. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit. if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc1436a/ltc1437a will begin to skip cycles. the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. therefore this limit should be avoided. figure 12. minimum on-time vs inductor ripple current because of the sensitivity of the ltc1436a/ltc1437a current comparator when operating close to the minimum on-time limit, it is important to prevent stray magnetic flux generated by the inductor from inducing noise on the current sense resistor, which may occur when axial type cores are used. by orienting the sense resistor on the radial axis of the inductor (see figure 13), this noise will be minimized. inductor ripple current (% of i max ) 0 200 minimum on-time (ns) 250 300 350 400 recommended region for min on-time and max efficiency 10 20 30 40 1435a f12 50 60 70
21 ltc1436a ltc1436a-pll/ltc1437a applicatio n s i n for m atio n wu u u efficiency. for example, in a 20v to 5v application, 10ma of intv cc current results in approximately 3ma of v in current. this reduces the midcurrent loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the mosfet, inductor and current shunt. in continuous mode the average output current flows through l and r sense , but is chopped between the topside main mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 0.05 w , r l = 0.15 w and r sense = 0.05 w , then the total resis- tance is 0.25 w . this results in losses ranging from 3% to 10% as the output current increases from 0.5a to 2a. i 2 r losses cause the efficiency to drop at high output currents. 4. transition losses apply only to the topside mosfet(s), and only when operating at high input voltages (typi- cally 20v or greater). transition losses can be esti- mated from: transition loss = 2.5(v in ) 1.85 (i max )(c rss )(f) other losses including c in and c out esr dissipative losses, schottky conduction losses during dead-time and inductor core losses, generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out immediately shifts by an amount equal to ( d i load )(esr), where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out which generates a feedback error signal. the regulator loop then acts to return v out to its steady-state value. during this recovery time v out can be monitored for overshoot or ringing, which would indicate a stability problem. the i th external components shown in the figure 1 circuit will provide adequate com- pensation for most applications. l inductor 1435a f08 figure 13. allowable inductor/r sense layout orientations efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc1436a/ltc1437a circuits: ltc1436a/ ltc1437a v in current, intv cc current, i 2 r losses and topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table which excludes mosfet driver and control currents. v in current results in a small (< 1%) loss which increases with v in . 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. it is for this reason that the adaptive power output stage switches to a low q t mosfet during low current operation. by powering extv cc from an output-derived source, the additional v in current resulting from the driver and control currents will be scaled by a factor of duty cycle/
22 ltc1436a ltc1436-pll-a/ltc1437a applicatio n s i n for m atio n wu u u a second, more severe transient is caused by switching in loads with large (>1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately 25(c load ). thus a 10 m f capacitor would require a 250 m s rise time, limiting the charging current to about 200ma. automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. but before you connect, be advised: you are plugging into the supply from hell. the main battery line in an automo- bile is the source of a number of nasty potential transients, including load dump, reverse battery, and double battery. load dump is the result of a loose battery cable. when the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse battery is just what it says, while double battery is a consequence of tow-truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 14 is the most straightfor- ward approach to protect a dc/dc converter from the ravages of an automotive battery line. the series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. note that the transient suppressor should not conduct during double battery operation, but must still clamp the input voltage below breakdown of the converter. although the ltc1436a/ltc1437a have a maxi- mum input voltage of 36v, most applications will be limited to 30v by the mosfet bv dss . design example as a design example, assume v in = 12v (nominal), v in = 22v (max), v out = 1.6v, i max = 3a and f = 250khz, r sense and c osc can immediately be calculated: r mv a cpf sense osc == = ? ? ? ? ? = 100 3 0 033 13710 250 11 43 4 . .( ) w refering to figure 3, a 4.7 m h inductor falls within the recommended range. to check the actual value of the ripple current the following equation is used: d i v fl v v l out out in = ()( ) - ? ? ? ? 1 the highest value of the ripple current occurs at the maximum input voltage: d i v khz h v v a l = () - ? ? ? ? = 16 250 4 7 1 16 22 13 . . . . m the lowest duty cycle also occurs at maximum input voltage. the on-time during this condition should be checked to make sure it doesnt violate the ltc1436a/ ltc1437as minimum on-time and cause cycle skipping to occur. the required on-time at v in(max) is: t v vf v v khz ns on min out in max () () . = () () = ()( ) = 16 22 250 291 the d i l was previously calculated to be 1.3a, which is 43% of i max . from figure 12, the ltc1436a/ltc1437as minimum on-time at 43% ripple is about 235ns. there- fore, the minimum on-time is sufficient and no cycle skipping will occur. figure 14. automotive application protection 1436 f14 50a i pk rating ltc1436a ltc1437a transient voltage suppressor general instrument 1.5ka24a v in 12v
23 ltc1436a ltc1436a-pll/ltc1437a applicatio n s i n for m atio n wu u u the power dissipation on the topside mosfet can be easily estimated. choosing a siliconix si4412dy results in: r ds(on) = 0.042 w , c rss = 100pf. at maximum input voltage with t (estimated) = 50 c: p v v cc v a pf khz mw main = () + () - () [] () + ()()( )( ) = 16 22 3 1 0 005 50 25 0 042 2 5 22 3 100 250 88 2 185 . .. . . w the most stringent requirement for the synchronous n-channel mosfet occurs when v out = 0 (i.e. short circuit). in this case the worst-case dissipation rises to: pi r sync sc avg ds on = ? ? + () ( ) ( ) 2 1 d with the 0.033 w sense resistor i sc(avg) = 4a will result, increasing the si4412dy dissipation to 950mw at a die temperature of 105 c. c in is chosen for an rms current rating of at least 1.5a at temperature. c out is chosen with an esr of 0.03 w for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: vri amv oripple esr l = () = () = dw 003 13 39 .. p-p pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1436a/ltc1437a. these items are also illustrated graphically in the layout diagram of figure 15. check the following in your layout: 1. are the signal and power grounds segregated? the ltc1436a/ltc1437a signal ground pin must return to the (C) plate of c out . the power ground connects to the source of the bottom n-channel mosfet, anode of the schottky diode, and (C) plate of c in , which should have as short lead lengths as possible. 2. does the ltc1436a/ltc1437a v osense pin connect to the (+) plate of c out ? in adjustable applications, the resistive divider r1/r2 must be connected between the (+) plate of c out and signal ground. the 100pf capaci- tor should be as close as possible to the ltc1436a/ ltc1437a. 3. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor be- tween sense + and sense C should be as close as possible to the ltc1436a/ltc1437a. 4. does the (+) plate of c in connect to the drain of the topside mosfet(s) as closely as possible? this capaci- tor provides the ac current to the mosfet(s). 5. is the intv cc decoupling capacitor connected closely between intv cc and the power ground pin? this ca- pacitor carries the mosfet driver peak currents. 6. keep the switching node sw away from sensitive small- signal nodes. ideally, the switch node should be placed at the furthest point from the ltc1436a/ltc1437a. 7. route the pllin line away from boost and sw pins to avoid unwanted pickup (boost and sw pins have high dv/dts). 8. sgnd should be used exclusively for grounding exter- nal components on pll lpf, c osc , i th , lbi, sfb, v osense and auxfb pins. 9. if operating close to the minimum on-time limit, is the sense resistor oriented on the radial axis of the induc- tor? see figure 13.
24 ltc1436a ltc1436-pll-a/ltc1437a + + + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pll lpf c osc run/ss lbo lbi i th sfb sgnd v prog v osense nc sense sense + auxon pllin por boost tgl sw tgs v in intv cc drv cc bg pgnd extv cc auxdr auxfb r lp r c c lp c c 1000pf open 100pf r1 c out r sense l1 4.7 m f c b 0.1 m f d b m3 d1 ext clock ltc1437a + + m1 m2 1437 f15 c in r2 output divider required with v prgm open bold lines indicate high current paths 5v ext v cc connection aux on/off c ss c c2 c osc v in v out figure 15. ltc1437a layout diagram applicatio n s i n for m atio n wu u u
25 ltc1436a ltc1436a-pll/ltc1437a typical applicatio n s u intel mobile cpu vid core power converter with 1.8v i/o supply 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 + + + + + c osc run/ss lbo lbi i th sfb sgnd v prog v osense sense sense + auxon por boost tgl sw tgs v in intv cc bg pgnd extv cc auxdr auxfb c osc 68pf c in 22 m f 35v 2 c sec 3.3 m f 35v c out 100 m f 10v 2 c c 510pf m1 s4412dy m2 si4412dy mbrs140t3 sgnd (pin 7) 1436 ta02 t1 10 m h 1:1 47k r sense 0.025 w mbrs1100t3 v in 4.5v to 28v 2n2905a v out2 5v 100ma v out 3.3v 4a m3 irlml2803 4.7 m f 3.3 m f r8 180k r7 56k r6 430k r5 100k 51pf 0.1 m f cmdsh-3 ltc1436a 1000pf aux on/off r c 10k c c2 51pf c ss 0.1 m f 24v ltc1436a 3.3v/4a fixed output with 5v auxiliary output 1436 ta09 + + c c 220pf 100pf r c 10k c ss 0.1 f c osc 43pf 1000pf aux on/off l1 3.3 h r sense 0.015 v in 4.5v to 22v v core 1.3v to 2v 7a v in2 3.3v sgnd (pin 6) 0.22 f 0.1 f 10k c in 22 f 35v x2 4.7 f m1 si4410dy m2 si4410dy *d b d1 mbrs140t3 c c2 1000pf 4.7 + c out 820 f 4v 2 v cc fb 0 12 vid ltc1706-19 from p 3 7 36 5 812 4 gnd sense v in 2 3 4 7 6 8 intv cc c osc external frequency synchronization sgnd v prog pll lpf pllin v osense tgl tgs sw auxdr pgnd bg boost run/ss i th sense + auxon auxfb sense ltc1436a-pll v i/o 1.8v 150ma m3 irlml2803 18 124 0.1 f 21 19 20 17 22 16 15 13 9 10 11 12 47k 10.5k 20k 51pf mmbt2907l 47 f 4v** *cmdsh-3 **input capacitor may not be necessary if 3.3v supply has sufficient capacitance 47 f 4v
26 ltc1436a ltc1436-pll-a/ltc1437a typical applicatio n s u ltc1436a-pll 2.5v/5v adjustable output with foldback current limiting and 5v auxiliary output 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 + + pll lpf c osc run/ss i th sfb sgnd v prog v osense sense sense + auxon auxfb pllin por boost tgl sw tgs v in intv cc bg pgnd extv cc auxdr c lp 0.01 m f c in 22 m f/35v 2 ext clock + c out1 100 m f 10v 2 c c 510pf m1 si4412dy m2 si4412dy mbrs140t3 sgnd (pin 6) 1436 ta04 t1 10 m h 1:2.2 47k r sense 0.025 w v in 4.5v to 28v v out2 12v 0.5a v out1 3.3v 4a m3 irlml2803 m4, irll014 4.7 m f 0.01 m f 11.3k 1%k 100k 1%k 0.1 m f cmdsh-3 cmdsh-3 ltc1436a-pll 1000pf comp on/off r c, 10k r lp 10k c c2 51pf c ss 0.1 m f c osc 68pf comparator + c sec 3.3 m f 35v t1: dale lpe6562-a092 ltc1436a-pll 5v/3a fixed output with 12v/200ma auxiliary output and uncommitted comparator 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 + + + + + pll lpf c osc run/ss i th sfb sgnd v prog v osense sense sense + auxon auxfb pllin por boost tgl sw tgs v in intv cc bg pgnd extv cc auxdr c lp 0.01 m f c in 22 m f 35v 2 ext clock c sec 3.3 m f 35v c out 100 m f 10v 2 r1 100k 1% r2 35.7k 1% c c 510pf open m1 si4410dy m2 si4410dy mbrs140t3 sgnd (pin 6) 1436 ta03 t1 10 m h 1:1.6 47k r sense 0.02 w mbrs1100t3 v in 4.5v to 24v zetex fzt749 v out2 5v 0.2a i th (pin 4) 1n4148 v out 2.5v 5a 24v m3 irlml2803 4.7 m f 3.3 m f r8 180k r7 56k r6 430k r5 100k 51pf 0.1 m f cmdsh-3 ltc1436a-pll 100 w 100 w 1000pf aux on/off r c, 10k r lp 10k c c2 51pf c ss 0.1 m f c osc 68pf 100pf 100pf
27 ltc1436a ltc1436a-pll/ltc1437a g28 ssop 0694 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 13 0.397 ?0.407* (10.07 ?10.33) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn24 (ssop) 0595 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.0075 ?0.0098 (0.191 ?0.249) 0.053 ?0.069 (1.351 ?1.748) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.009 (0.102 ?0.249) 0.025 (0.635) bsc 0.337 ?0.344* (8.560 ?8.737) 12 3 4 5 6 7 8 9 10 11 12 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 17 18 19 20 21 22 23 24 15 14 13 gn package 24-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) dimensions in inches (millimeters) unless otherwise noted. package descriptio n u typical applicatio n s u ltc1436a-pll low noise high efficiency 5v/1a regulaor 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 + + + + pll lpf c osc run/ss i th sfb sgnd v prog v osense sense sense + auxon auxfb pllin por boost tgl sw tgs v in inv cc bg pgnd extv cc auxdr c lp 0.01 m f c in 22 m f 35v ext clock 250khz sfb = 0v: continuous mode sfb = 5v: burst enabled c out 100 m f 10v r1 240k 1% r2 56k 1% 100pf 100pf c c 510pf m1 irf7201 m2 irf7201 mbrs140t3 sgnd (pin 6) 1436 ta07 l1 50 m h 47k r sense 0.1 w v in 5.5v to 28v zetex fmmt549 heat sink v out 5v 1a v1 6.3v m3 irlml2803 4.7 m f 22 m f r8 180k 1% r7 56k 1% 51pf 0.1 m f cmdsh-3 ltc1436a-pll 1000pf v out on/off r c, 10k r lp 10k c c2 51pf c ss 0.1 m f c osc 39pf g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640)
28 ltc1436a ltc1436-pll-a/ltc1437a 14367afa lt/tp 0898 rev a 2k ? printed in usa ? linear technology corporation 1996 typical applicatio n u ltc1437a 5v/3a fixed output with 12v auxiliary output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 + + + + pll lpf c osc run/ss lbo lbi i th sfb sgnd v prog v osense nc sense sense + auxon pllin por boost tgl sw tgs v in inv cc drv cc bg pgnd extv cc auxdr auxfb c lp 0.01 m f c in 22 m f 35v 2 ext clock c sec 3.3 m f 35v c out 100 m f 10v 2 c c 510pf int v cc m1 irf7403 m2 irf7403 mbrs140t3 sgnd (pin 8) 1436 ta06 t1 22 m h 1:2.2 47k r sense 0.03 w mbrs1100t3 v in 5.5v to 28v mmbt2907 v out2 12v 0.2a v out 5v 3a 24v m3 irlml2803 4.7 m f 3.3 m f r6 1m t1: dale lpe6562-a092 r5 100k 0.1 m f cmdsh-3 ltc1437a 1000pf aux on/off r c 10k r lp 10k c c2 51pf c ss 0.1 m f c osc 39pf + related parts part number description comments ltc1142hv/ltc1142 dual high efficiency synchronous step-down switching regulators dual synchronous, v in 20v ltc1148hv/ltc1148 high efficiency step-down switching regulator controllers synchronous, v in 20v ltc1159 high efficiency synchronous step-down switching regulator synchronous, v in 40v, for logic threshold fets lt ? 1375/lt1376 1.5a, 500khz step-down switching regulators high frequency, small inductor, high efficiency switchers, 1.5a switch ltc1430 high power step-down switching regulator controller high efficiency 5v to 3.3v conversion at up to 15a ltc1435a high efficency, low noise synchronous step-down 16-pin narrow so and ssop switching regulator ltc1438/ltc1439 dual high efficiency, low noise, synchronous step-down full-featured dual controllers switching regulators lt1510 constant-voltage/ constant-current battery charger 1.3a, li-ion, nicd, nimh, pb-acid charger ltc1538-aux dual high efficiency, low noise, synchronous step-down 5v standby in shutdown switching regulator ltc1539 dual high efficiency, low noise, synchronous step-down 5v standby in shutdown switching regulator ltc1706-19 vid voltage programmer intel mobile pentium ? ii compliant pentium is a registered trademark of intel corp. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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